There is an ever-increasing demand for ever-denser semiconductor memories, and customers continue to purchase these memories in ever-greater quantities, even as the number of bits per chip quadruples (approximately) every three years. Increasingly higher densities are required, at ever lower costs, to meet the needs of the marketplace.
Semiconductor nonvolatile memories may be divided into two categories: (1) those in which data is permanently written during the manufacturing process and whose contents cannot be subsequently changed, called “mask ROMs” or “factory programmed ROMs”; (2) those in which data may be supplied after the finished memory device leaves the factory. This latter category is called “field programmable memories” because their contents may be written, by the user, when the semiconductor memory chip is deployed to its final application, “in the field”.
Field programmable memories are further subdivided into “write once” memories and “write/erase/rewrite” memories. Those written once are referred to as “PROM” (programmable read only memories) or “OTP ROM” (one time programmable read only memories). And those memories that provide write/erase/rewrite capabilities have been referred to as “UVEPROM” (ultraviolet erasable programmable read only memories) or “EEPROM” (electrically erasable programmable read only memories) or “Flash EEPROM” (fast and flexible EEPROMs). In contrast, the contents of mask ROMs are permanently stored during manufacture, therefore mask ROMs are not erasable and are effectively “write only once, at the factory” memories.
Field programmable memories are much more flexible than mask ROMs, since they allow system product makers to inventory a single general part-type for many applications, and to personalize (program the memory contents of) this one part-type in numerous different ways, much later in the system product flow. This flexibility lets system manufacturers more easily adapt to fluctuations in demand among different system products, and to update or revise system products without the expense of scrapping (discarding) existing inventories of pre-programmed mask ROMs, but this flexibility has a cost. Field programmable memories generally achieve lower densities (fewer bits per chip) and higher cost (larger price per bit) than mask ROMs. Customers would prefer to buy something that offers the flexibility and convenience of a field programmable memory, while achieving the cost and density of a mask ROM. Unfortunately, such a device has yet not been available.
There were two reasons why mask ROMs were denser and cheaper than field programmable memories. First, since mask ROMs do not support erase or rewrite functions, their peripheral circuits need not contain any dedicated circuitry or 1/0 terminals for input-data steering, for write timing, or for write control. Thus the peripheral circuits of a mask ROM may be smaller than those of a field programmable nonvolatile memory. This reduces the die size of a mask ROM, compared to the die size of a field programmable nonvolatile memory, allowing more mask ROM chips to fit on a semiconductor wafer, which lowers costs. Second, since mask ROMs are written only at the factory, their memory cells may be designed and optimized for read operations exclusively, and generally their memory cells consist of only a single circuit element (e.g. a single MOS transistor). In contradistinction, the memory cell of a field programmable nonvolatile memory must include support for write operations. Therefore, field programmable memory cells generally contained more than one circuit element: generally a second tunnel oxide floating gate, or a write/erase series transistor, is added to the single MOS transistor needed for reading. The extra element(s) in the field programmable cell consume additional silicon area, making the memory cell area larger than the area of a mask ROM memory cell. Thus the density of field programmable nonvolatile memories has been lower than the density of mask ROMs.
Field programmable memories having write/erase/rewrite capabilities offer yet more flexibility. They permit product upgrades, field reconfiguration, and enable a host of new applications such as digital photography, solid state disks, et cetera. Unfortunately, these devices have generally suffered from lower density and higher cost than one-time programmable memories.
Turning now to the design of the memory cell used in these memories, most nonvolatile memory cells have employed semiconductor devices such as MOS field-effect transistors, junction transistors, or junction diodes, built in a planar monocrystalline semiconductor substrate. This approach allows only very limited integration vertically into the third dimension (i.e. perpendicular to the plane of the substrate), since each memory cell contains some elements built in the substrate. In the late 1990's one time programmable 3D memory arrays were devised using diodes and anti-fuse type programmable elements. Specific examples of such devices can be seen in U.S. patents and published applications to Matrix Semiconductor. These patents and published applications include U.S. Pat. Nos. 6,034,882; 6,185,122; 6,483,736; 6,525,953; 6,642,603; 6,780,711; 6,853,049; 6,984,561 and 6,995,422, and 2005/0158950 the disclosures of which are hereby incorporated by reference. These 3D devices may be fabricated by methods described in “Vertical p-i-n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM” by S. B. Herner, et al., published in IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, May 2004, p. 271-273.
These 3D memory arrays are very useful for what they bring to the field programmable memory market, but they lack a key feature which is very desirable. For all of their cost and space savings, these memory devices are often not reprogrammable, other than those of the published application 2005/0158950 cited above. That is none of the memory elements can be erased or rewritten. Thus, there is a need in the art to enhance the 3D memory arrays of the prior art by using reprogrammable memory elements. Unfortunately, as discussed above most reprogrammable memory devices on the market are composed of additional silicon semiconductor devices that do not stack 3D.
Methods for making the polydiode stack reprogrammable are described in U.S. Published Patent Application no. 2005/0158950 published Jul. 21, 2005. However, because the reprogrammable material deteriorates at the higher temperatures required to crystallize the polydiode (e.g. 500-700° C.), there is a need for a lower cost 3D stackable approach with reprogrammable memory.